Memory systems are known which include a main memory and a high speed cache for temporarily storing data, the data in the cache being readily accessible by a processor or microprocessor. If a computer is designed so that more than one device has access to the cacheable memory, cache coherency must be maintained to keep the cache contents consistent with memory. Consider the following situation: a central processing unit (CPU) is using a write-through cache to temporarily store data from main memory while an alternate bus master also has access to the data in main memory. If the bus master writes new data into a memory location which also happens to reside in the CPU cache, then an invalidation cycle must occur to let the CPU know that the data in its cache is no longer valid. An invalidation cycle, also known as a "snoop" cycle, must occur simultaneously with the bus master write cycle. Such action will eliminate any latency between the time that new data is written into main memory and the time that the CPU knows that its cache location is invalid.
If a bus master performs several write cycles to main memory, each cache line affected must be invalidated in the cache. As long as the basic snoop cycle is shorter in duration than a memory write cycle, there is no problem in performing consecutive snoop cycles. However, if the length of the basic snoop cycle is longer than a memory write cycle, one of two situations might occur: 1) cache coherency (contents of cache being the same as corresponding contents of main memory) will not be maintained because the snoop control mechanism cannot keep up with the bus master write cycles, or 2) the bus master is forced to run slower cycles so that the snoop cycles can be completed. If the snoop cycles can be pipelined, then such situations can be avoided.